1. Technical Field
The present invention relates generally to integrated circuits and, in particular, to 3D inter-stratum connectivity robustness.
2. Description of the Related Art
A three-dimensional (3D) stacked chip includes two or more electronic integrated circuit chips (referred to as strata or stratum) stacked one on top of the other. The strata are connected to each other with inter-strata interconnects that could use C4 or other technology, and the strata could include through-silicon vias (TSVs) to connect from the front side to the back side of the strata. The strata could be stacked face-to-face or face-to-back where the active electronics can be on the “face” side of a particular stratum.
In conventional integrated circuit (IC) chip design, a layout versus schematic (LVS) apparatus and a set of methodology checking rules (e.g., design rule check (DRC)) are used to perform physical integrated circuit verification which paves a path for flawless integration and packaging. As is known, LVS is an electronic design automation (EDA) verification tool that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design. In 3D stacked integrated circuit assemblies, however, there are scenarios where, even with each chip passing its own LVS and methodology checks, the interface signals, clocks or powers can be unintentionally shorted to each other or left unconnected (open) when all chips are assembled into a 3D stack. For example, two terminal pins of the same net from two face-to-face or face-to-back strata may not be electrically connected because they are not physically aligned to each other and 3D assemblies do not allow for intermediate wires to connect them. As a result, there is a demand to implement a 3D design methodology to extend IC verification beyond current single-chip LVS and methodology tool capabilities.